The present invention relates to a semiconductor memory and, more particularly, to a technique which may be applied to semiconductor memories, for example, dynamic type RAMs (Random Access Memories) or the like.
One type of dynamic RAM has a timing control circuit (i.e., a timing generating circuit). This timing control circuit forms timing signals and internal control signals which are used to control the operation of each circuit block in a dynamic type RAM on the basis of a plurality of control signals which are supplied externally.
The dynamic type RAM that has a timing control circuit is described, for example, in "Hitachi IC Memory Data Book", Hitachi, Ltd., Sept. 1983, pp. 251-259.
The dynamic RAM of the type described above is provided with a plurality of external terminals through which are inputted and outputted the above-described control signals, address signals, storage data or the like. The number of these external terminals installed is minimized, so that there is no room to provide external terminals for outputting the states of signals transmitted to internal nodes in a control circuit such as the above-described timing control circuit, that is, timing signals, internal control signals or the like. Accordingly, functional testing that is carried out to confirm the operation of the timing control circuit must be realized by repeating an indirect method that an appropriate memory cell is actually brought into a select state and a predetermined write or read operation is executed in relation to this memory cell to judge whether or not the write or read operation has been successfully effected.
Semiconductor memories such as dynamic type RAMs tend to be provided with highly advanced functions and multifunctional properties and, as a result, the circuit configuration of a control circuit, for example, the above-described timing control circuit, is increasingly complicated. Further, as a result of the achievement of highly advanced and multifunctional semiconductor memories such as dynamic type RAMs, there has been an increase in the number of product testing items. Accordingly, when the above-described conventional testing method is adopted as it is, a disadvantageously long testing time is required, and it may be impossible to inspect a special additional function. In addition, despite the complexity of the control circuits, e.g., the above-described timing control circuit, it is impossible to externally confirm the states of signals transmitted to internal nodes in the control circuits. This leads to the problem that it is impossible to accurately carry out failure analysis and measurement of operating margin or the like after the completion of products. Even when write data and read data are coincident with each other and therefore the result of a test carried out on the basis of the conventional testing method is judged to be normal, there may be a small defect which may cause a failure. For example, the waveform of a predetermined internal signal measured after the completion of a product may discord with the waveform expected at the time of designing. The inventors of the present invention have found that a small defect such as that described above leads to a failure such as erroneous reading of stored data, when, for example, the use conditions of the product become worse. Accordingly, it is necessary to measure the waveform of an internal signal after the completion of each product.